1. Invention
The present invention generally relates to a successive approximation register analog to digital converter (SAR-ADC), especially to a SAR-DAC including an analog integrator.
2. Description of the Prior Art
A sample and hold circuit for a traditional touch panel may be saturated due to large instantaneous noise. The instantaneous noise may come from a power supply, a conductive substance touching the panel, a human body approaching the panel or the like, causing a difference between a sensing value of a sensor in the touch panel and a value sampled and held by the S/H circuit. In other words, the S/H circuit must discard the value sampled and held this time, and then perform S/H operation on the sensing value of the sensor in the touch panel again. As such, not only the operation time for the S/H circuit is increased, and it may not be possible to measure the original sensing value of the sensor in the touch panel in the next S/H operation. (For example, assuming in the previous S/H operation the S/H circuit has obtained 40% of the sensing value of the sensor in the touch panel, but this value is discarded due to saturation caused by the instantaneous noise, then the S/H circuit may only obtain the remaining 60% of the sensing value of the sensor in the current S/H operation).
Moreover, the S/H circuits for traditional touch panels typically operate only in the positive or negative pulses, so 50% of the clock cycles are wasted. Alternatively, some S/H circuits employ inverters so that they can operate in both the positive and negative pulses (e.g. negative pulses are converted into positive pulses via the inverter, and a S/H circuit operating in the positive pulses can now operate in what originally were the negative pulses). However, transmission time delays in the inverters may result in pulse overlap in high-speed S/H circuits. For example, assuming that after a negative pulse is converted into a positive pulse via an inverter a 5% transmission time delay is introduced to the pulse, then the pulse time of the last 5% of the waveform of this positive pulse will overlap the pulse time of the first 5% of the waveform of the next positive pulse. This pulse overlap problem is more noticeable and severe particularly in high-frequency S/H circuits or inverters with large transmission time delays, which may even result in S/H circuit disorder. Alternatively, some S/H circuits employ inverters to directly perform phase conversion on the results sampled and held by the S/H circuits before using them. However, control clocks of the inverters and the transmission time delays are still problems that are yet to be solved.
In view of these shortcomings, the present invention thus provides a multi-stage S/H circuit for positive and negative pulse cycles that alleviates the saturation issue caused by the instantaneous noise in the traditional S/H circuits and addresses the pulse overlap problem in the traditional S/H circuits for positive and negative pulse cycles, while achieving S/H operations for positive and negative pulse cycles.
Among traditional ADC, SAR-ADC is one of common ADC. In the design of SAR-ADC, a binary tree structure is formed by a capacitor array. Utilizing a comparator and a control logic, the SAR-ADC can deliver an output bits which has nth order of 2. As mentioned above, ordinary S/H circuit also comprises capacitor used to integrate the input analog signal.
Since the capacitor occupies quite large die area, if capacitors can be shared by S/H circuit and the attached SAR-ADC, some die area could be spared for decreasing manufacture cost.